An FPGA-based readout chip emulator for the CMS ETL detector upgrade
نویسندگان
چکیده
Abstract We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The uses Intel Cyclone 10 GX FPGA to emulate digital functions of four Readout Chips (ETROCs). Based on actual ETROC design, firmware is implemented and verified. being used design verification system development.
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ژورنال
عنوان ژورنال: Journal of Instrumentation
سال: 2023
ISSN: ['1748-0221']
DOI: https://doi.org/10.1088/1748-0221/18/02/c02031